When manufacturing housed electronic components, unhoused (semiconductor) chips, or what are known as “bare dies”, are placed on a substrate. Within the scope of what is known as the “embedded Wafer Level Package” (eWLP) process, one or more chips per package are for this purpose placed with the active side down onto an adhesive film disposed on the substrate. A multiplicity of set-down chips are then potted using a compound made of plastic, which later constitutes the housing. The entire potted product is then fired at high pressure and then released from the substrate or the adhesive film. In the following process steps, the chips are then contacted, possibly electrically connected, and solder balls serving as electrical connection contacts are applied. At the end, the entire processed potted product is sawn into individual components or otherwise separated.
More specifically, an eWLP is a housing model for integrated circuits in which the electrical connection contacts are produced on a wafer artificially manufactured from chips and potting compound. All necessary processing steps for forming a housing are thus carried out on the artificial wafer. Compared with conventional housing technologies, in which what is known as “wire bonding” is used, this allows the production of an extremely small and flat housing having excellent electrical and thermal properties with particularly low production costs. With this technology, components can be produced for example as a ball grid array (BGA).
A further integration approach known in microelectronics is the production of what are known as system-in-package (SiP) modules. In the case of an SIP process, passive and active components and also further components are produced from a plurality of (semiconductor) chips, and these chips are then set down by means of a placement process on a substrate, wherein the substrate can be an epoxy printed circuit board material, an adhesive film or a metal foil, for example. The set-down chips are then combined by means of known construction and connection techniques in a housing, often referred to as an IC package. Necessary electrical connections between the individual chips can be provided for example by means of bond wires, wherein other connection principles such as conductive thin films on side edges of the chips or feedthroughs are also possible.
Chips that are still unhoused are handled within the scope of an eWLP process or when manufacturing SIP modules typically by means of a (modified) placement machine compared with the known Surface Mount Technology. A placement machine of this type has a placement head, by means of which the chips are placed on the substrate in question at predefined placement positions. Here, the requirements on the positional accuracy of the placement are particularly high. A positional accuracy or placement accuracy of 15 μm/3σ or more accurate is currently required both for an eWLP process and for the production of SIP modules, wherein σ (sigma) is the standard deviation for the placement position. Due to the increasing miniaturization of electronic components, it is anticipated that even greater requirements will be placed on the placement accuracy in the future.
When manufacturing both eWLP and SIP modules, an extremely large number of chips are placed on a relatively large-area substrate for efficiency reasons. Here, substrates can also be so large or long that they must be moved along a transport direction during the course of a placement process taking a very long time. Where appropriate, a clocked placement in a placement region of the placement machine in question might also be necessary in the case of a particularly long substrate. Here, different parts of the substrate to be equipped are introduced into the placement region in succession (possibly with a certain spatial overlap), and are equipped there with chips. In this regard, it is clear that large or long substrates make it additionally difficult to observe a high placement accuracy.
The object of the present invention is to specify a placement machine and a method for equipping a substrate with unhoused semiconductor chips which enables a particularly high placement accuracy, even with the use of large substrates.